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 PD - 97104
IRFI4321PBF
Applications l Motion Control Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l Hard Switched and High Frequency Circuits Benefits l Low RDSON Reduces Losses l Low Gate Charge Improves the Switching Performance l Improved Diode Recovery Improves Switching & EMI Performance l 30V Gate Voltage Rating Improves Robustness l Fully Characterized Avalanche SOA
HEXFET(R) Power MOSFET
VDSS RDS(on) typ. max. ID
D
150V 12.2m: 16m: 34A
D
G
G
D
S
S
TO-220AB Full-Pak D S
G
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS EAS (Thermally limited) TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current c Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy d Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
Max.
34 21 140 46 0.37 30 170 -55 to + 150 300 10lbxin (1.1Nxm) Typ. --- --- Max. 2.73 65
Units
A
W W/C V mJ C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case f Junction-to-Ambient f Units C/W
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1
6/23/06
IRFI4321PBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
150 --- --- 3.0 --- --- --- --- --- --- 190 12.2 --- --- --- --- --- 0.8 --- 16 5.0 20 1.0 100 -100 --- V
Conditions
VGS = 0V, ID = 250A
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) IDSS IGSS RG(int) Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
--- mV/C Reference to 25C, ID = 1mAe m VGS = 10V, ID = 20A e V A nA VDS = VGS, ID = 250A VDS = 150V, VGS = 0V VGS = 20V VGS = -20V
mA VDS = 150V, VGS = 0V, TJ = 125C
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
50 --- --- --- --- --- --- --- --- --- --- --- 73 24 20 18 29 27 20 4440 390 84 --- 110 --- --- --- --- --- --- --- --- --- pF ns S nC ID = 20A VDS = 75V VGS = 10V e VDD = 75V ID = 20A RG = 2.5 VGS = 10V e VGS = 0V VDS = 50V = 1.0MHz
Conditions
VDS = 50V, ID = 20A
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) c Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- --- 86 310 6.7 34 140 1.3 130 470 --- A A V ns nC A
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 20A, VGS = 0V e ID = 20A VR = 128V, di/dt = 100A/s e
G S D
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.85mH RG = 25, IAS = 20A, VGS =10V. Part not recommended for use above this value.
Pulse width 400s; duty cycle 2%. R is measured at TJ approximately 90C
2
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IRFI4321PBF
1000
TOP VGS 15V 10V 8.0V 7.0V 6.5V 6.0V 5.5V 5.0V
1000
TOP VGS 15V 10V 8.0V 7.0V 6.5V 6.0V 5.5V 5.0V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
100
BOTTOM
10
10
1
5.0V 60s PULSE WIDTH Tj = 150C
5.0V
0.1 0.1 1
60s PULSE WIDTH Tj = 25C
10 100
1 0.1 1 10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
3.0
Fig 2. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
VDS = 25V
ID, Drain-to-Source Current()
100
ID = 20A
2.5
60s PULSE WIDTH TJ = 150C
VGS = 10V
2.0
10
(Normalized)
1.5
TJ = 25C
1
1.0
0.5
0.1 3.0 4.0 5.0 6.0 7.0
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
7000 6000 5000 4000 3000 2000 1000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd
Fig 4. Normalized On-Resistance vs. Temperature
20
VGS, Gate-to-Source Voltage (V)
ID= 20A VDS = 120V VDS= 75V VDS= 30V
16
C, Capacitance (pF)
Ciss
12
Coss
8
4
Crss
0 1 10 100 1000
0 0 20 40 60 80 100 120 QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFI4321PBF
1000
1000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA LIMITED BY R DS (on)
ISD , Reverse Drain Current (A)
100
100 1msec 10 10msec 1 Tc = 25C Tj = 150C Single Pulse 0.1 0.1 1.0 DC 100sec
TJ = 150C
10
1
TJ = 25C VGS = 0V
0.1 0.2 0.4 0.6 0.8 1.0
10.0
100.0
1000.0
VSD , Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
V(BR)DSS , Drain-to-Source Breakdown Voltage
35 30 190
Fig 8. Maximum Safe Operating Area
180
ID , Drain Current (A)
25 20 15 10 5 0 25 50 75 100 125 150
170
160
150
140 -60 -40 -20 0 20 40 60 80 100 120 140 160
TC , CaseTemperature (C)
TJ , Junction Temperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
5.0
Fig 10. Drain-to-Source Breakdown Voltage
700
EAS, Single Pulse Avalanche Energy (mJ)
600 500 400 300 200 100 0
4.0
ID 4.6A 5.4A BOTTOM 20A
TOP
Energy (J)
3.0
2.0
1.0
0.0 40 60 80 100 120 140 160
25
50
75
100
125
150
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFI4321PBF
10
Thermal Response ( Z thJC )
1
D = 0.50 0.20 0.10 0.05 0.02 0.01
J J 1 1
0.1
R1 R1 2
R2 R2
R3 R3 C 3
Ri (C/W)
(sec)
2
3
Ci= i/Ri Ci= i/Ri
0.312941 0.000381 1.187255 0.219458 1.231176 2.895
0.01
SINGLE PULSE ( THERMAL RESPONSE )
0.001 1E-006 1E-005 0.0001 0.001 0.01
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.1 1 10
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
Avalanche Current (A)
10
0.01 0.05
1
0.10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C.
0.1
0.01 1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
180 160
EAR , Avalanche Energy (mJ)
140 120 100 80 60 40 20 0 25 50
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 20A
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
150
75
100
125
Starting TJ , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFI4321PBF
6.0
40
VGS(th), Gate threshold Voltage (V)
5.0
ID = 1.0A ID = 1.0mA ID = 250A
IRRM - (A)
30
4.0
20
3.0
10
2.0
IF = 33A VR = 128V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
1.0 -75 -50 -25 0 25 50 75 100 125 150 175
0
TJ , Temperature ( C )
dif / dt - (A / s)
Fig 16. Threshold Voltage Vs. Temperature
40
Fig. 17 - Typical Recovery Current vs. dif/dt
3200 2800
30
2400
20
QRR - (nC)
IF = 50A VR = 128V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
IRRM - (A)
2000 1600 1200 800 400 0 IF = 33A VR = 128V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
10
0
dif / dt - (A / s)
dif / dt - (A / s)
Fig. 18 - Typical Recovery Current vs. dif/dt
3200 2800 2400
Fig. 19 - Typical Stored Charge vs. dif/dt
QRR - (nC)
2000 1600 1200 800 400 0 IF = 50A VR = 128V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFI4321PBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
LD VDS
Fig 22b. Unclamped Inductive Waveforms
+
VDD D.U.T VGS Pulse Width < 1s Duty Factor < 0.1%
90%
VDS
10%
VGS
td(on) tr td(off) tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id Vds Vgs
L
0
DUT 1K
VCC
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRFI4321PBF
TO-220AB Full-Pak Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Full-Pak Part Marking Information
EXAMPLE: T HIS IS AN IRFI840G WIT H AS S EMBLY LOT CODE 3432 AS S EMBLED ON WW 24, 2001 IN T HE AS S EMBLY LINE "K" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER
IRFI840G 124K 34 32
Note: "P" in as s embly line pos ition indicates "Lead-Free"
DAT E CODE YEAR 1 = 2001 WEEK 24 LINE K
TO-220AB Full-Pak packages are not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 06/06
8
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